A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set

Authors:
Mitsuo Ikeda;Tsuneo Okubo;Tetsuya Abe;Yoshinori Ito;Yutaka Tashiro;Ryota Kasai
Affiliations:
NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi, 243-01, Japan;NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi, 243-01, Japan;NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi, 243-01, Japan;NTT Human Interface Laboratories, 1-2356, Take, Yokosuka, 238-03, Japan;NTT Human Interface Laboratories, 1-2356, Take, Yokosuka, 238-03, Japan;NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi, 243-01, Japan
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 3
Cited 5

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Hardware-Software Cosynthesis for Microcontrollers

IEEE Design & Test
Software estimation using a generic-processor model

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Am embedded system case study: the firm ware development environment for a multimedia audio processor

DAC '97 Proceedings of the 34th annual Design Automation Conference
An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance analysis and optimization of latency insensitive systems

Proceedings of the 37th Annual Design Automation Conference
SuperENC: MPEG-2 Video Encoder Chip

IEEE Micro
Floorplan assisted data rate enhancement through wire pipelining: a real assessment

Proceedings of the 2005 international symposium on Physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract