Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
SuperENC: MPEG-2 Video Encoder Chip
IEEE Micro
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput-driven floorplanning with wire pipelining
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning With Wire Pipelining in Adaptive Communication Channels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asynchronous Solutions for Nanomagnetic Logic Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. The goal is achieved through the encapsulation of synchronous logic blocks in wrappers that communicate via a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from excessive performance penalty in terms of throughput, or lack of generality. The authors present an adaptive version of an LIP that outperforms previous "static" implementations, as demonstrated through two relevant study cases: a microprocessor and an MPEG encoder, whose components are made insensitive to the latencies of their interconnections through a newly developed wrapper. This article also features an informal exposition of the theoretical basis of adaptive LIPs as well as implementation details.