Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Coping with Latency in SOC Design
IEEE Micro
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrency in Synchronous Systems
Formal Methods in System Design
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Process Algebraic View of Latency-Insensitive Systems
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
System-on-chip designs are composed of modules working at different clock frequencies. These modules will communicate using control and data events. However, they cannot be directly connected as their events will not be synchronised. In this paper, we give a formal framework for a latency insensitive interconnect which can be used for assembling such modules. The interface guarantees that the events are sent in correct order and there is no loss of information. Also, any change in the latency of event transmission by the sender or un-availability of the receiver to receive an event is handled correctly. We prove properties of the interface using the tagged-signal framework and illustrate the construction of a mixed-timing system.