Abstraction of Clocks in Synchronous Data-Flow Systems
APLAS '08 Proceedings of the 6th Asian Symposium on Programming Languages and Systems
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Research Letters in Signal Processing
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synchronous elasticization at a reduced cost: utilizing the ultra simple fork and controller merging
Proceedings of the International Conference on Computer-Aided Design
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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We formally define--at the stream transformer level--a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove fundamental compositionality results. The paper contributes to bridging the gap between the theory of latency-insensitive systems and the correct implementation of efficient control structures for them.