Coping with Latency in SOC Design
IEEE Micro
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Performance analysis of concurrent systems with early evaluation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
Scheduling Synchronous Elastic Designs
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Latency insensitive (LI) designs can tolerate arbitrary computation and communication latencies. Synchronous elasticization converts an ordinary clocked design into LI. It uses communication protocols such as the Synchronous Elastic Flow (SELF). Comparing to its lazy implementations, eager SELF has no combinational cycles and can provide performance advantage. Yet, it uses eager forks (EForks) consuming more area and power. This paper demonstrates that EForks can be redundant. A novel ultra simple fork (USFork) implementation is introduced. The conditions under which an EFork will behave exactly the same as a USFork (from the protocol perspective) are formally derived. The paper also investigates the conditions under which multiple SELF controllers can be merged to further decrease the area and power overhead (as long as the physical placement allows). The flow has been integrated in a fully automated tool, HGEN. Hybrid GENerator (HGEN) selectively replaces redundant EForks with USForks and, optionally, merges equivalent controllers. HGEN uses 6thSense tool as an embedded verification engine. Comparing to the methodology used in published work on a MiniMIPS processor case study, HGEN shows up to 34.3% and 25.4% savings in area and power due to utilizing USForks. It also shows at least 32% saving in the number of EForks in s382 ISCAS benchmark. More reduction is possible if the physical placement allows for controller merging. Thanks to the advance in synchronous verification technology, HGEN runs within a few minutes (for all this paper examples). This makes the proposed approach suitable for tight time-to-market constraints.