Coping with Latency in SOC Design
IEEE Micro
Non-massive, Non-high Performance, Distributed Computing: Selected Issues
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Some Synchronization Issues When Designing Embedded Systems from Components
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Issues in Implementing Latency Insensitive Protocols
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2004 international symposium on Physical design
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A New System Design Methodology for Wire Pipelined SoC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient embedded software design with synchronous models
Proceedings of the 5th ACM international conference on Embedded software
Distributing synchronous programs using bounded queues
Proceedings of the 5th ACM international conference on Embedded software
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Formal Methods in System Design
Concurrency in Synchronous Systems
Formal Methods in System Design
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Performance analysis of concurrent systems with early evaluation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Electronic Notes in Theoretical Computer Science (ENTCS)
Dataflow Architectures for GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
Separate Compilation of Polychronous Specifications
Electronic Notes in Theoretical Computer Science (ENTCS)
Compositionality of Statically Scheduled IP
Electronic Notes in Theoretical Computer Science (ENTCS)
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Composing heterogeneous reactive systems
ACM Transactions on Embedded Computing Systems (TECS)
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
Compositional design of isochronous systems
Proceedings of the conference on Design, automation and test in Europe
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on Petri Nets and Other Models of Concurrency I
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell
Electronic Notes in Theoretical Computer Science (ENTCS)
Electronic Notes in Theoretical Computer Science (ENTCS)
Desynchronisation Technique Using Petri Nets
Electronic Notes in Theoretical Computer Science (ENTCS)
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Retiming and recycling for elastic systems with early evaluation
Proceedings of the 46th Annual Design Automation Conference
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
A Verification Approach for GALS Integration of Synchronous Components
Electronic Notes in Theoretical Computer Science (ENTCS)
A Functional Programming Framework for Latency Insensitive Protocol Validation
Electronic Notes in Theoretical Computer Science (ENTCS)
Bounded dataflow networks and latency-insensitive circuits
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A real-time architecture design language for multi-rate embedded control systems
Proceedings of the 2010 ACM Symposium on Applied Computing
Loosely time-triggered architectures for cyber-physical systems
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic microarchitectural pipelining
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
A unifying view of loosely time-triggered architectures
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Research Letters in Signal Processing
Throughput optimization for latency-insensitive system with minimal queue insertion
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mechanism of resource virtualization in RCS for multitask stream applications
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Cross clock-domain TDM virtual circuits for networks on chips
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Abstraction-based performance verification of NoCs
Proceedings of the 48th Design Automation Conference
Compositional design of isochronous systems
Science of Computer Programming
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Synchronous elasticization at a reduced cost: utilizing the ultra simple fork and controller merging
Proceedings of the International Conference on Computer-Aided Design
Symbolic performance analysis of elastic systems
Proceedings of the International Conference on Computer-Aided Design
Leveraging latency-insensitivity to ease multiple FPGA design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Static scheduling of latency insensitive designs with Lucy-n
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A Scheduling Strategy for Synchronous Elastic Designs
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
MPC'12 Proceedings of the 11th international conference on Mathematics of Program Construction
Periodic scheduling of marked graphs using balanced binary words
Theoretical Computer Science
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Quantifying the cost and benefit of latency insensitive communication on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be “recovered” by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies