Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Free choice Petri nets
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Concurrency in Synchronous Systems
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
Transition systems of elementary net systems with localities
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Step persistence in the design of GALS systems
PETRI NETS'13 Proceedings of the 34th international conference on Application and Theory of Petri Nets and Concurrency
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In this paper we consider the problem of desynchronising modular synchronous specifications for their realisation into GALS architectures and obtaining simple wrappers that are efficiently synthesisable using existing synthesis tools. The systems are modeled using Petri nets (PN) and the desynchronisation technique is based on the theory of PN Localities. The firing semantics of a globally synchronous system is characterised by maximal firing of input and output transitions. The partitioning of a synchronous system is achieved by unbundling the input transitions and allowing the output transitions to fire in maximal steps, in order to enable asynchronous communication in a distributed environment. Our model satisfies the two essential correctness properties, namely, semantics preservation and deadlock prevention, during the shift from maximal firing semantics, followed by synchronous systems, to standard interleaving semantics for input transitions and maximal step firing semantics for output transitions, followed by GALS architectures. The formation of localities is supported by adding internal signals which are necessary for building wrappers in the localities that will generate local clock enables. These wrappers can be subsequently synthesised using PN based synthesis tools.