DVB-DSNG modem high level synthesis in an optimized latency insensitive system context

Authors:
P. Bomel;N. Abdelli;E. Martin;A.-M. Fouilliart;E. Boutillon;P. Kajfasz
Affiliations:
LESTER Laboratory, CNRS FRE2734, UBS University, Lorient Cedex, France;THALES Communications, Colombes Cedex, France;LESTER Laboratory, CNRS FRE2734, UBS University, Lorient Cedex, France;THALES Communications, Colombes Cedex, France;LESTER Laboratory, CNRS FRE2734, UBS University, Lorient Cedex, France;THALES Communications, Colombes Cedex, France
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

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Abstract

This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al.. This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists in IP encapsulation into a new wrapper model containing a synchronization processor which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT [1], a high-level synthesis tool.