A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Coping with Latency in SOC Design
IEEE Micro
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A New System Design Methodology for Wire Pipelined SoC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
Necessary and sufficient conditions for deterministic desynchronization
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
A Verification Approach for GALS Integration of Synchronous Components
Electronic Notes in Theoretical Computer Science (ENTCS)
A Functional Programming Framework for Latency Insensitive Protocol Validation
Electronic Notes in Theoretical Computer Science (ENTCS)
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP blocks. Their approach overcomes the problem of long latencies of global interconnects in deep-submicron technologies, while still maintaining much of the inherent simplicity of synchronous design. In particular, wires whose latency is greater than a clock cycle are segmented using "relay stations," and IP blocks are made robust to arbitrary communication delays.This paper shows, however, that significant extensions are needed to make latency-insensitive systems useful for the practical design of large-scale SoC's. In particular, this paper proposes three extensions. The .rst extension allows each synchronous module to treat its input and output channels in a much more flexible manner, i.e., with greater decoupling. The second extension generalizes inter-module communication from point-to-point channels to more complex networks of arbitrary topologies. Finally, the third extension is to target multi-clock SoC's. The net impact of our extensions is the potential for improved throughput, reduced power consumption, and greater flexibility in design.