Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Coping with Latency in SOC Design
IEEE Micro
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On-Chip Transparent Wire Pipelining
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Performance analysis of concurrent systems with early evaluation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early evaluation for performance enhancement in phased logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamically control their operations. In particular, a shell stalls a pearl whenever new valid data are not available on its input channels. We study how functional independence conditions (FIC) can be applied to the performance optimization of a latency-insensitive system by avoiding unnecessary stalling of their pearls. We present a novel circuit design of a generic shell template that can exploit FICs. We describe an automatic procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the logic structure of its corresponding pearl and does not require any input from the designers. We implemented the proposed technique within the logic synthesis tool ABC and we use it to complete various experiments that demonstrate its performance benefits and limited overhead. In particular, we completed the semi-custom design of a system-on-chip (SoC), an ultra-wideband baseband transmitter, using a state-of-the-art 90nm technology process. To the best of our knowledge this represents the first report on the complete latency-insensitive design of a real-world SoC.