Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
Quantifying the cost and benefit of latency insensitive communication on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip designers. Latency-insensitive design (LID) has been proposed as a "correct-by-construction" design methodology to cope with this problem. In this paper we present the design and implementation of a new class of interface circuits to support LID that offers substantial performance improvements with limited area overhead with respect to previous designs proposed in the literature. This claim is supported by the experimental results that we obtained completing semi-custom implementations of the three designs with a 90nm industrial standard-cell library. We also report on the formal verification of our design: using the NuSMV model checker we verified that the RTL synthesizable implementations of our LID interface circuits (relay stations and shells) are correct refinements of the corresponding abstract specifications according to the theory of LID.