Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Information and Computation
Coping with Latency in SOC Design
IEEE Micro
Some Synchronization Issues When Designing Embedded Systems from Components
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
From multi-clocked synchronous processes to latency-insensitive modules
Proceedings of the 5th ACM international conference on Embedded software
Concurrency in Synchronous Systems
Formal Methods in System Design
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Information and Computation
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Electronic Notes in Theoretical Computer Science (ENTCS)
Compositional design of isochronous systems
Proceedings of the conference on Design, automation and test in Europe
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As Globally Asynchronous and Locally Synchronous (GALS) based System-on-chip (SoC) are gaining importance, a special case of GALS when the global clocking is preserved, but the interconnect delays of multiple clock cycles are to be tolerated has also been proposed, and used. In some cases, such designs, known as Latency-Insensitive Protocol (LIP) based SoC integration are also general enough to work when the global clocking is not present. In either case, the protocols are complex, and many optimized implementations of such protocols need verification that indeed they work correctly with respect to the specification of the system. Usually the specification of the system is fully globally clocked with negligible interconnect delays, so that the specification can be first implemented as synchronous design with traditional tools. GALS or LIP refinements are then applied to tolerate the multi-cycle interconnect delays, or fully asynchronous interconnect communication, as the case may be. Verifying that such refinements are correctness preserving, researchers have used model checking in the past. In this paper, we present static analysis based framework for such verification. Our framework makes use of the Polychrony framework and associated semantic analysis techniques, in the form of endo-isochrony. We show a number of LIP protocols to preserve the correctness with respect to their fully synchronous specifications using our framework. We believe, designers can verify LIP implementations with clever optimizations using our framework much more readily than when using model checking.