From multi-clocked synchronous processes to latency-insensitive modules

Authors:
Jean-Pierre Talpin;Dimitru Potop-Butucaru;Julien Ouy;Benoit Caillaud
Affiliations:
INRIA - IRISA, Cedex, France;INRIA - IRISA, Cedex, France;INRIA - IRISA, Cedex, France;INRIA - IRISA, Cedex, France
Venue:
Proceedings of the 5th ACM international conference on Embedded software
Year:
2005

Citing 1
Cited 6

Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications

ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design

Polychronous mode automata

EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Separate Compilation of Polychronous Specifications

Electronic Notes in Theoretical Computer Science (ENTCS)
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications

Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Compositional design of isochronous systems

Proceedings of the conference on Design, automation and test in Europe
Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

Electronic Notes in Theoretical Computer Science (ENTCS)
Compositional design of isochronous systems

Science of Computer Programming

Quantified Score

Hi-index	0.00

Visualization

Abstract

We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This involves the synthesis of asynchronous wrappers that drive the synchronous clocks of the modules and perform input reading in such a fashion as to preserve, in a certain sense, the global properties of the system. Our approach is based on the theory of weakly endochronous systems, which gives criteria guaranteeing the existence of simple and efficient asynchronous wrappers. We focus on the transformation (by means of added signalling) of the synchronous modules of a multiclock synchronous specification into weakly endochronous modules, for which simple and efficient wrappers exist.