Proceedings of the 5th ACM international conference on Embedded software
From multi-clocked synchronous processes to latency-insensitive modules
Proceedings of the 5th ACM international conference on Embedded software
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synchronization after design refinements with sensitive delay elements
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Composing heterogeneous reactive systems
ACM Transactions on Embedded Computing Systems (TECS)
An Analysis of the Composition of Synchronous Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
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We introduce a model for the representation of asynchronous implementations of synchronous specifications. The model covers classical implementations, where a notion of global synchronization is preserved by means of signaling, and globally asynchronous, locally synchronous (GALS) implementations where the global clock is removed. Our model offers a unifiedframework for reasoning about two essential correctness properties of an implementation: the preservation of semantics and the absence of deadlocks.