Programming and Verifying Real-Time Systems by Means of the Synchronous Data-Flow Language LUSTRE
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
Minimum area retiming with equivalent initial states
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Formal Verification of Dynamic Properties in an Aerospace Application
Formal Methods in System Design
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Automatic generation of equivalent architecture model from functional specification
Proceedings of the 41st annual Design Automation Conference
System Level Design and Verification Using a Synchronous Language
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Formal Methods in System Design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at a high level of abstraction. In synchronous models, a local refinement increasing the delay in a single computation block may affect the functionality of the entire model. We provide a synchronization algorithm that preserves the system's functionality after design refinements, by using additional synchronization delays and making some delays sensitive to their input values. The refined and synchronized model stays latency equivalent to the original model. The advantages of our approach are the following: (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, specific communication protocols, wrapper circuits around computation blocks or schedulers.