Proof, language, and interaction
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synchronization after design refinements with sensitive delay elements
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Formal Functional Verification of Device Drivers
VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Formal Verification of Gate-Level Computer Systems
CSR '09 Proceedings of the Fourth International Computer Science Symposium in Russia on Computer Science - Theory and Applications
Compositional modeling for data-centric business applications
SC'08 Proceedings of the 7th international conference on Software composition
Implementing constrained cyber-physical systems with IEC 61499
ACM Transactions on Embedded Computing Systems (TECS)
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Synchronous languages such as Esterel, Lustre, Signal, andothers were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) and recent system-level languages (SystemC, System Verilog), they have well defined formal semantics,which facilitate bug avoidance using correct-by-constructioncompilation and verification techniques.The tutorial will demonstrate what the synchronous language offers for the modeling, design, analysis and implementation of systems that comprise hardware and software.It will be based on Esterel. Esterel models have proved tobe useful for rapid design space exploration and verificationat system level, without resorting to detailed implementation and slow bit-level event-based simulation. We show how to model control-dominated IP blocks at a higher levelof abstraction and how to use the target C code or RTL inconjunction with other system-level tools. Case studies include examples of design space exploration by synthesizing equivalent hardware or software from the same Esterel description, with formal verification of safety properties such as bus protocol conformance. We conclude with a review of future research directions.