Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
An approach to systems verification
Journal of Automated Reasoning
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
IEEE Software
System Level Design and Verification Using a Synchronous Language
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dealing with I/O Devices in the Context of Pervasive System Verification
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Putting it all together – Formal verification of the VAMP
International Journal on Software Tools for Technology Transfer (STTT) - A View from Formal Methods 2003 (pp 301-354); Special Section on Recent Advances in Hardware Verification (pp 355-447)
Formal Functional Verification of Device Drivers
VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Efficient Bit-Level Model Reductions for Automated Hardware Verification
TIME '08 Proceedings of the 2008 15th International Symposium on Temporal Representation and Reasoning
Journal of Automated Reasoning
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
On the verification of memory management mechanisms
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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We present the formal verification of a gate-level computer system, in which a complex processor and external devices run in parallel. The system specification is an instruction set architecture with concurrently running visible devices. To the best of our knowledge this is the first formal treatment of integrating devices into a gate-level computer system.