On the verification of memory management mechanisms

Authors:
Iakov Dalinger;Mark Hillebrand;Wolfgang Paul
Affiliations:
Computer Science Dept., Saarland University, Saarbrücken, Germany;Computer Science Dept., Saarland University, Saarbrücken, Germany;Computer Science Dept., Saarland University, Saarbrücken, Germany
Venue:
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Year:
2005

Citing 11
Cited 16

A computational logic handbook

A computational logic handbook
Microprocessor design verification

Journal of Automated Reasoning
A mechanically verified language implementation

Journal of Automated Reasoning
A mechanically verified code generator

Journal of Automated Reasoning
Kit and the short stack

Journal of Automated Reasoning
Computer Architecture: Complexity and Correctness

Computer Architecture: Complexity and Correctness
Processor Verification with Precise Exeptions and Speculative Execution

CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
PVS: A Prototype Verification System

CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Dealing with I/O Devices in the Context of Pervasive System Verification

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes

SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
On the correctness of operating system kernels

TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics

Dealing with I/O Devices in the Context of Pervasive System Verification

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of Lower System Layers in Automotive Systems

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes

SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
A Logic for Virtual Memory

Electronic Notes in Theoretical Computer Science (ENTCS)
CVM -- A Verified Framework for Microkernel Programmers

Electronic Notes in Theoretical Computer Science (ENTCS)
Towards a Worldwide Verification Technology

Verified Software: Theories, Tools, Experiments
Mapped Separation Logic

VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Verified Process-Context Switch for C-Programmed Kernels

VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Balancing the Load

Journal of Automated Reasoning
Formal Verification of Gate-Level Computer Systems

CSR '09 Proceedings of the Fourth International Computer Science Symposium in Russia on Computer Science - Theory and Applications
Types, Maps and Separation Logic

TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
On the architecture of system verification environments

HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Realistic worst-case execution time analysis in the context of pervasive system verification

Program analysis and compilation, theory and practice
Pervasive verification of an OS microkernel: inline assembly, memory consumption, concurrent devices

VSTTE'10 Proceedings of the Third international conference on Verified software: theories, tools, experiments
Lyrebird: assigning meanings to machines

SSV'10 Proceedings of the 5th international conference on Systems software verification
Towards the pervasive verification of automotive systems

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods

Quantified Score

Hi-index	0.00

Visualization

Abstract

We report on the design and formal verification of a complex processor supporting address translation by means of a memory management unit (MMU). We give a paper and pencil proof that such a processor together with an appropriate page fault handler simulates virtual machines modeling user computation. These results are crucial steps towards the seamless verification of entire computer systems.