A new fault-tolerant algorithm for clock synchronization
Information and Computation
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Dealing with I/O Devices in the Context of Pervasive System Verification
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of Lower System Layers in Automotive Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Formal Model of Lower System Layers
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
On the verification of memory management mechanisms
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Easy parameterized verification of biphase mark and 8n1 protocols
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Proving Fairness and Implementation Correctness of a Microkernel Scheduler
Journal of Automated Reasoning
On the architecture of system verification environments
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Model checking the FlexRay physical layer protocol
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
Complete formal hardware verification of interfaces for a FlexRay-like bus
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
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We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP processor.We get a time triggered distributed real-time system by connecting several such ECU's via a common bus. We define a programming model for such a system at the instruction set architecture (ISA) level and prove that it is correctly implemented at the gate level. The proof combines theories of processor correctness, communication systems, program correctness and realistic worst-case execution time (WCET) analysis into a single unified mathematical theory.