Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
IEEE Transactions on Software Engineering
Formal verification of time-triggered systems
Formal verification of time-triggered systems
A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Efficient Bit-Level Model Reductions for Automated Hardware Verification
TIME '08 Proceedings of the 2008 15th International Symposium on Temporal Representation and Reasoning
Realistic worst-case execution time analysis in the context of pervasive system verification
Program analysis and compilation, theory and practice
Automated verification and refinement for physical-layer protocols
Formal Aspects of Computing
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We report the first complete formal verification of a timetriggered bus interface at the gate and register level. We discuss hardware models for multiple clock domains and we review known results and proof techniques about the essential components of such bus interfaces: among others serial interfaces, clock synchronization and bus control. Combining such results into a single proof leads to an amazingly subtle theory about the realization of direct connections between units (as assumed in existing correctness proofs for components of interfaces) by properly controlled time-triggered buses. It also requires an induction arguing simultaneously about bit transmission across clock domains, clock synchronization and bus control.