A Mechanically Checked Proof of a Multiprocessor Result via a Uniprocessor View
Formal Methods in System Design
Proceedings of the 37th Annual Design Automation Conference
Towards a mechanically checked theory of computation: the ACL2 project
Logic-based artificial intelligence
Formal Methods in System Design
Verifying the FM9801 Microarchitecture
IEEE Micro
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Comparison of Two Verification Methods for Speculative Instruction Execution
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of Explicitly Parallel Microprocessors
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Results of the Verification of a Complex Pipelined Machine Model
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Elementary Microarchitecture Algebra
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Microarchitecture Verification by Compositional Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Rewriting for Symbolic Execution of State Machine Models
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verifying a Simple Pipelined Microprocessor Using Maude
WADT '01 Selected papers from the 15th International Workshop on Recent Trends in Algebraic Development Techniques
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A Practical Methodology for Verifying Pipelined Microarchitectures
IEEE Design & Test
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dealing with I/O Devices in the Context of Pervasive System Verification
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computers
Realistic worst-case execution time analysis in the context of pervasive system verification
Program analysis and compilation, theory and practice
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Formally defining and verifying master/slave speculative parallelization
FM'05 Proceedings of the 2005 international conference on Formal Methods
A generic network on chip model
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
On the verification of memory management mechanisms
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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