Handbook of theoretical computer science (vol. B)
The SECD microprocessor: a verification case study
The SECD microprocessor: a verification case study
Handbook of logic in computer science (vol. 1)
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Algebraic models of microprocessors: the correctness and verification of a simple computer
MDS '95 Proceedings of the second international conference on Mathematics of dependable systems II
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
Towards an Algebraic Specification of the Java Virtual Machine
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
A Tutorial on Using PVS for Hardware Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
An Algebraic Model of Correctness for Superscalar Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Hardware Verification Using PVS
Formal Hardware Verification - Methods and Systems in Comparison
A Correctness Model for Pipelined Multiprocessors
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Systematic Formal Verification of Interpreters
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
On abstractions for timing analysis in the K framework
FOPARA'11 Proceedings of the Second international conference on Foundational and Practical Aspects of Resource Analysis
| Hi-index | 0.00 |
We consider the verification of a simple pipelined microprocessor in Maude, by implementing an equational theoretical model of systems. Maude is an equationally-based language, with an efficient term rewriting implementation, and effective meta-level tools. Microprocessors and other systems are modelled as iterated maps operating in time over some state-set, and are related by means of data and abstraction maps, and correctness is reduced to state exploration by the choice of an appropriate initialization function, ensuring/enforcing consistency of the initial state.