Techniques for verifying superscalar microprocessors

Verification of electronic systems

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Toward formalizing a validation methodology using simulation coverage

DAC '97 Proceedings of the 34th annual Design Automation Conference

Verifying correct pipeline implementation for microprocessors

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Formal verification of pipeline control using controlled token nets and abstract interpretation

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

A Practical Methodology for the Formal Verification of RISC Processors

Formal Methods in System Design

Formal verification in hardware design: a survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction

Proceedings of the 37th Annual Design Automation Conference

Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)

Boolean satisfiability with transitivity constraints

ACM Transactions on Computational Logic (TOCL)

Formal Verification of Out-of-Order Execution with Incremental Flushing

Formal Methods in System Design

Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability

Formal Methods in System Design

Verifying the FM9801 Microarchitecture

IEEE Micro

Algebraic Models of Superscalar Microprocessor Implementations: A Case Study

Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters

Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors

TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic

CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Formal Verification of Designs with Complex Control by Symbolic Simulation

CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

A Framework for Microprocessor Correctness Statements

CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions

TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods

EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

Verifying a Simple Pipelined Microprocessor Using Maude

WADT '01 Selected papers from the 15th International Workshop on Recent Trends in Algebraic Development Techniques

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

Journal of Symbolic Computation

A Practical Methodology for Verifying Pipelined Microarchitectures

IEEE Design & Test

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Efficient formal verification of pipelined processors with instruction queues

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Efficient translation of boolean formulas to CNF in formal verification of microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Using positive equality to prove liveness for pipelined microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Comparison of schemes for encoding unobservability in translation to SAT

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Formal Verification of Pipelined Microprocessors with Delayed Branches

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Monolithic verification of deep pipelines with collapsed flushing

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Modelling and verification of superscalar Micro-architectures functional approach

ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers

Symbolic program analysis using term rewriting and generalization

Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design

A method for debugging of pipelined processors in formal verification by correspondence checking

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors

ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering

Automatic formal verification of reconfigurable DSPs

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional units

ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering

Automatic formal verification of multithreaded pipelined microprocessors

Proceedings of the International Conference on Computer-Aided Design

Automatic formal verification of liveness for pipelined processors with multicycle functional units

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods