Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ACL2 Theorems About Commercial Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation: An ACL2 Approach
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation of the JEM1 Microprocessor
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
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A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification time without giving false negatives. The equivalence checker is able to cope with different numbers of control steps and different implementational details in the two descriptions to be compared.