Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Formal Verification of Out-of-Order Execution with Incremental Flushing
Formal Methods in System Design
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verifying a Simple Pipelined Microprocessor Using Maude
WADT '01 Selected papers from the 15th International Workshop on Recent Trends in Algebraic Development Techniques
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
A general decomposition strategy for verifying register renaming
Proceedings of the 41st annual Design Automation Conference
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Several methods have recently been proposed for verifying processors with out-of-order execution. These methods use intermediate abstractions to decompose the verification process into smaller steps. Unfortunately, the process of manually creating intermediate abstractions is very laborious. We present an approach that dramatically reduces the need for an intermediate abstraction, so that only the scheduling logic of the implementation is abstracted. After the abstraction, we apply an enhanced incremental-flushing approach to verify the remaining circuitry by comparing the processor description against itself in a slightly simpler configuration. By induction, we demonstrate that any reachable configuration is equivalent to the simplest possible configuration. Finally, we prove correctness on the simplest configuration. The approach is illustrated with a simple example of an out-of-order execution core.