Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
Communication and concurrency
Model checking
Verification of a simple pipelined machine model
Computer-Aided reasoning
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Simple Characterization of Stuttering Bisimulation
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Formal verification of an advanced pipelined machine
Formal verification of an advanced pipelined machine
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
A parameterized benchmark suite of hard pipelined-machine-verification problems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Monolithic verification of deep pipelines with collapsed flushing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Electronic Notes in Theoretical Computer Science (ENTCS)
Towards the Formal Verification of a Java Processor in Event-B
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Challenge of Hardware-Software Co-verification
Verified Software: Theories, Tools, Experiments
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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We present a compositional reasoning framework based on refinement for verifying that pipelined machines satisfy the same safety and liveness properties as their instruction set architectures. Our framework consists of a set of convenient, easily-applicable, and complete compositional proof rules. We show that our framework greatly extends the applicability of decision procedures by verifying a complex, deeply pipelined machine that state-of-the-art tools cannot currently handle. We discuss how our framework can be added to the design cycle and highlight what arguably is the most important benefit of our approach over current methods, that the counterexamples generated are much simpler, as bugs are isolated to a particular step in the composition proof.