Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
Microprocessor design verification
Journal of Automated Reasoning
Common LISP: the language (2nd ed.)
Common LISP: the language (2nd ed.)
Functional instantiation in first-order logic
Artificial intelligence and mathematical theory of computation
Communication and concurrency
Piton: a mechanically verified assembly-level language
Piton: a mechanically verified assembly-level language
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Model checking
High-speed, analyzable simulators
Computer-Aided reasoning
Verification of a simple pipelined machine model
Computer-Aided reasoning
RTL verification: a floating-point multiplier
Computer-Aided reasoning
Design verification of a safety-critical embedded verifier
Computer-Aided reasoning
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Structured Theory Development for a Mechanized Logic
Journal of Automated Reasoning
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode
Formal Methods in System Design
ACL2 Theorems About Commercial Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation of the JEM1 Microprocessor
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Simple Characterization of Stuttering Bisimulation
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Transforming the Theorem Prover into a Digital Design Tool: From Concept Car to Off-Road Vehicle
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Formal verification of an advanced pipelined machine
Formal verification of an advanced pipelined machine
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Monolithic verification of deep pipelines with collapsed flushing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Ordinal Arithmetic: Algorithms and Mechanization
Journal of Automated Reasoning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Towards the Formal Verification of a Java Processor in Event-B
Electronic Notes in Theoretical Computer Science (ENTCS)
Refinement for Pipelining in Event-B
Electronic Notes in Theoretical Computer Science (ENTCS)
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In this chapter, we describe the ACL2 theorem proving system and show how it can be used to model and verify hardware using refinement. This is a timely problem, as the ever-increasing complexity of microprocessor designs and the potentially devastating economic consequences of shipping defective products has made functional verification a bottleneck in the microprocessor design cycle, requiring a large amount of time, human effort, and resources [1, 58]. For example, the 1994 Pentium FDIV bug cost Intel $475 million and it is estimated that a similar bug in the current generation Intel Pentium processor would cost Intel $12 billion [2].