Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Journal of Symbolic Computation
Coverage-oriented verification of banias
Proceedings of the 40th annual Design Automation Conference
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Verifying a gigabit ethernet switch using SMV
Proceedings of the 41st annual Design Automation Conference
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Smart diagnostics for configurable processor verification
Proceedings of the 42nd annual Design Automation Conference
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
XFM: An incremental methodology for developing formal models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDD-based verification of scalable designs
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A method for the evaluation of behavioral fault models
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Depth-driven verification of simultaneous interfaces
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
XFM: extreme formal method for capturing formal specification into abstract models
Formal methods and models for system design
Practical methods in coverage-oriented verification of the merom microprocessor
Proceedings of the 43rd annual Design Automation Conference
System on Chips optimization using ABV and automatic generation of SystemC codes
Microprocessors & Microsystems
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
MMV: a metamodeling based microprocessor validation environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
A general method to make multi-clock system deterministic
Proceedings of the Conference on Design, Automation and Test in Europe
Post-silicon debugging for multi-core designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
Fast and generalized polynomial time memory consistency verification
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Parallel QBF Solving with Advanced Knowledge Sharing
Fundamenta Informaticae - RCRA 2009 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Developing a new leading edge IA-32 micro-processor is an immensely complicated undertaking. In the case of the Pentium© 4 processor, the microarchitecture is significantly more complex than any previous IA-32 microprocessor and the implementation borrows almost nothing from any previous implementation. This paper describes how we went about the task of finding bugs in the Pentium© 4 processor design prior to initial silicon, and what we found along the way.