Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Verification of configurable processor cores
Proceedings of the 37th Annual Design Automation Conference
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Coverage-oriented verification of banias
Proceedings of the 40th annual Design Automation Conference
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Probabilistic regression suites for functional verification
Proceedings of the 41st annual Design Automation Conference
| Hi-index | 0.00 |
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica's latest configurable processor. Conventional simulation-based verification methodologies that employ assembly programs for testing cannot easily link the diagnostic program to the test-bench for interactive control, consequently resulting in weaker coverage. ETC links the diagnostic program execution and the test-bench functions, thereby increasing the flexibility and power of the diagnostics to create more complex corner cases in fewer simulation cycles and with smaller code size. This method also enables dynamic self-checking and dynamic coverage analysis by either passing or failing the diagnostic based on the coverage goal, or terminating runaway random diagnostics much earlier. The presented simulation results show that ETC augments verification in two major areas: the creation of more maintainable, efficient, and smart diagnostics, and the reduction of the regression time. Some of the techniques presented in this paper can apply to non-processor verification methodologies as well.