Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential logic testing and verification
Sequential logic testing and verification
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Achieving maximum performance: a method for the verification of interlocked pipeline control logic
Proceedings of the 39th annual Design Automation Conference
Stimuli Generation with Late Binding of Values
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
Smart diagnostics for configurable processor verification
Proceedings of the 42nd annual Design Automation Conference
Simplifying the design and automating the verification of pipelines with structural hazards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
New methods and coverage metrics for functional verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Programming and Computing Software
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new test program generation tool, mVpGen, is developed for verifying pipeline design of microprocessors. The only inputs mVpGen requires are pipeline-behavior specifications; it automatically generates test cases at first from pipeline-behavior specifications and then automatically generates test programs corresponding to the test cases.Test programs for verifying complex pipeline behavior such as hazard and branch or hazard and exception, are generated. mVpGen has been integrated into a verification system for verifying RTL descriptions of a real microprocessor design and complex bugs that remained hidden in the RTL descriptions are detected.