Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
System-level power/performance analysis for embedded systems design
Proceedings of the 38th annual Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Hole analysis for functional coverage data
Proceedings of the 39th annual Design Automation Conference
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Framework for Design Space Exploration of Parameterized VLSI Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New methods and coverage metrics for functional verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A PD-based methodology to enhance efficiency in testbenches with random stimulation
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
| Hi-index | 0.00 |
In order to be reused in different applications Intellectual Properties (IP) are usually parameterized. On the one hand the extensive use of parameters enables users to customize IP to their needs in different applications. On the other hand a large number of parameters imposes new problems during IP qualification, verification and integration. This article gives an overview of the present work in the IP Qualification Project (IPQ) addressing problems due to IP parameterization. We are working on solutions to handle large parameter sets, to automatically implement parameter checking, and to improve functional coverage of the parameter space. Within this scope, a novel graph-based methodology to split the parameter space into orthogonal subspaces has been devised. On the basis of a formal description of parameters and their interdependences so-called Parameter Domain Graphs (PDG) are constructed. Relying on PDG, testbench components for assertion-based parameter checking are automatically generated. Furthermore, generation constraints for verification environments are derived and collection and analysis of functional coverage data is implemented.