A PD-based methodology to enhance efficiency in testbenches with random stimulation

Authors:
Carlos Ivan Castro Marquez;Marius Strum;Wang Jiang Chau
Affiliations:
University of São Paulo, Sao Paulo - SP - Brazil;University of São Paulo, Sao Paulo - SP - Brazil;University of São Paulo, Sao Paulo - SP - Brazil
Venue:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Year:
2009

Citing 6
Cited 1

Writing Testbenches: Functional Verification of HDL Models, Second Edition

Writing Testbenches: Functional Verification of HDL Models, Second Edition
Safe integration of parameterized IP

Integration, the VLSI Journal - Special issue: IP and design reuse
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)

Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Functional test selection based on unsupervised support vector analysis

Proceedings of the 45th annual Design Automation Conference

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuit's design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) model's functionality, applying sets of testcases. There are different techniques concerning testbenches operation, being the random stimulation an important approach, by which a huge number of testcases can be automatically created and applied. In testbench development, creation of random stimuli generators containing overlapping or invalid input parameter subspaces may occur, wasting computational time during testbench execution. In this work, we present a methodology to organize and apply random input stimuli by means of IP parameter domain, PD, formalism. The methodology provides the application of stimulus which: 1) belongs to the valid parameter subspace; 2) avoids repeated conditions; 3) covers the parameter subspaces uniformly. Moreover the methodology allows the automation of several tasks, making it efficient and less error-prone. Results on applying such a methodology are compared to cases where test vectors from the complete (unreduced, unorganized) verification space are generated manually, analyzing its relation to the coverage models specified for the design verification.