Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Verification strategy for integration 3G baseband SoC
Proceedings of the 40th annual Design Automation Conference
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
An automatic testbench generation tool for a SystemC functional verification methodology
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A PD-based methodology to enhance efficiency in testbenches with random stimulation
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Functional Verification of DMA Controllers
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
Journal of Electronic Testing: Theory and Applications
Contributions of model checking and CoFI methodology to the development of space embedded software
Empirical Software Engineering
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The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the main tasks in the design flow, aiming to certify the system functionality has been accomplished accordingly to the specification. A simulation based technique known as functional verification has been followed by the industry. In recent years, several articles in functional verification have been presented, focusing either on specific design verification experiments or on methods to improve and accelerate coverage reaching. In the first category, the majority of the papers are aimed to processors verification, while communication systems experiences were not such commonly reported. In the second category, different authors have proposed methodologies, which need an extensive and complex work by the verification engineer on tuning the acceleration algorithms to the specific design. In the present paper, we present a functional verification methodology applied to a Bluetooth Baseband adaptor core, described in SystemC RTL. Two techniques are considered, one following the traditional framework of applying random stimuli and checking functional coverage aspects; in the second one, a simple acceleration procedure, based on redundant stimuli filtering, is included. For both solutions, a hierarchical approach is adopted. We present several results comparing both solutions, showing the gain obtained in using the acceleration technique. Additionally, we show how results on a real testbench application environment correlate to the hierarchical verification approach taken.