IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Causality based generation of directed test cases
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
New methods and coverage metrics for functional verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Functional test selection based on unsupervised support vector analysis
Proceedings of the 45th annual Design Automation Conference
Verification of IP-Core Based SoC's
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automatic generation of functional coverage models from CTL
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
A PD-based methodology to enhance efficiency in testbenches with random stimulation
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
Journal of Electronic Testing: Theory and Applications
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Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.