Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Functional verification of the equator MAP1000 microprocessor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Design fault directed test generation for microprocessor validation
Proceedings of the conference on Design, automation and test in Europe
Clock domain crossing fault model and coverage metric for validation of SoC design
Proceedings of the conference on Design, automation and test in Europe
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test selection based on unsupervised support vector analysis
Proceedings of the 45th annual Design Automation Conference
Processor Description Languages
Processor Description Languages
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
MMV: a metamodeling based microprocessor validation environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Online selection of effective functional test programs based on novelty detection
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a functional coverage based test generation technique for pipelined architectures. The proposed methodology makes three important contributions. First, a general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. Second, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, test generation procedures are presented that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate that the number of test programs generated by our approach to obtain a fault coverage is an order of magnitude less than those generated by traditional random or constrained-random test generation techniques.