Integrated verification approach during ADL-driven processor design

Authors:
Anupam Chattopadhyay;Arnab Sinha;Diandian Zhang;Rainer Leupers;Gerd Ascheid;Heinrich Meyr
Affiliations:
Aachen University of Technology, Integrated Signal Processing Systems, 52056 Aachen, Germany;Department of Electrical Engineering, Princeton University, Princeton, NJ, USA;Aachen University of Technology, Integrated Signal Processing Systems, 52056 Aachen, Germany;Aachen University of Technology, Integrated Signal Processing Systems, 52056 Aachen, Germany;Aachen University of Technology, Integrated Signal Processing Systems, 52056 Aachen, Germany;Aachen University of Technology, Integrated Signal Processing Systems, 52056 Aachen, Germany
Venue:
Microelectronics Journal
Year:
2009

Citing 24
Cited 0

Automatic test program generation for pipelined processors

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic verification of pipelined microprocessors

DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient validity checking for processor verification

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Functional vector generation for HDL models using linear programming and 3-satisfiability

DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)
A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture Exploration for Embedded Processors with Lisa

Architecture Exploration for Embedded Processors with Lisa
Automatic verification of Pipelined Microprocessor Control

CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Improving Gate Level Fault Coverage by RTL Fault Grading

Proceedings of the IEEE International Test Conference on Test and Design Validity
Describing instruction set processors using nML

EDTC '95 Proceedings of the 1995 European conference on Design and Test
Graph-Based Functional Test Program Generation for Pipelined Processors

Proceedings of the conference on Design, automation and test in Europe - Volume 1
RTL Processor Synthesis for Architecture Exploration and Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 3
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

IEEE Design & Test
A Top-Down Methodology for Microprocessor Validation

IEEE Design & Test
Automatic Test Program Generation: A Case Study

IEEE Design & Test
Functional Coverage Driven Test Generation for Validation of Pipelined Processors

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Optimization Techniques for ADL-Driven RTL Processor Synthesis

RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Automatic functional test program generation for pipelined processors using model checking

HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Functional test generation using property decompositions for validation of pipelined processors

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Integrated Verification Approach during ADL-Driven Processor Design

RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Test generation games from formal specifications

Proceedings of the 43rd annual Design Automation Conference
Zchaff2004: an efficient SAT solver

SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Nowadays, architecture description languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of application specific instruction-set processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are only applied at register transfer level (RTL) or below. In the context of ADL-based ASIP design, this verification approach is often inconvenient and error-prone, since design and verification are done at different levels of abstraction. In this paper, this problem is addressed by presenting an integrated verification approach during ADL-driven processor design. Our verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design. We show the benefit of our approach by trapping errors in a pipelined SPARC-compliant processor architecture and in an application-specific DSP architecture.