Automatic functional test program generation for pipelined processors using model checking

Authors:
P. Mishra;N. Dutt
Affiliations:
Architectures & Compilers for Embedded Syst. (ACES), California Univ., Irvine, CA, USA;Architectures & Compilers for Embedded Syst. (ACES), California Univ., Irvine, CA, USA
Venue:
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Year:
2002

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Abstract

Formal techniques offer an opportunity to significantly reduce the cost of microprocessor verification. We propose a model checking based approach to automatically generate functional test programs for pipelined processors. We specify the processor architecture in an Architecture Description Language (ADL). The processor model is extracted from the ADL specification. Specific properties are applied to the processor model using SMV model checker to generate test programs. We applied this methodology on a single-issue DLX processor to demonstrate the usefulness of our approach.