Improving Test Quality Through Resource Reallocation
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Automatic functional test program generation for pipelined processors using model checking
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Factored planning: how, when, and when not
AAAI'06 Proceedings of the 21st national conference on Artificial intelligence - Volume 1
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Hi-index | 0.00 |
One of the challenges that processor level stimuli generators are facing is the need to generate stimuli that exercise microarchitectural mechanisms deep inside the verified processor. These scenarios require specific relations between the instructions participating in them. We present a new approach for processor-level scenario generation. The approach is based on creating an abstract constraint satisfaction problem, which captures the essence of the requested scenario. The generation of stimuli is done by interleaving between progress in the solution of the abstract CSP and generation of instructions. Compared with existing solutions of scenario generation, this approach yields improved coverage and reduced generation fail rate.