Random generation of combinatorial structures from a uniform
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Network-based heuristics for constraint-satisfaction problems
Artificial Intelligence
An incremental constraint solver
Communications of the ACM
Minimizing conflicts: a heuristic repair method for constraint satisfaction and scheduling problems
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Test program generation for functional verification of PowerPC processors in IBM
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Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Sufficient Condition for Backtrack-Free Search
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Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Branching programs and binary decision diagrams: theory and applications
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Solving the generalized mask constraint for test generation of binary floating point add operation
Theoretical Computer Science - Real numbers and computers
Constraint-Based Modeling of InterOperability Problems Using an Object-Oriented Approach
Proceedings of the Thirteenth Conference on Innovative Applications of Artificial Intelligence Conference
Constraint Slving for Test Case Generation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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Look-ahead value ordering for constraint satisfaction problems
IJCAI'95 Proceedings of the 14th international joint conference on Artificial intelligence - Volume 1
Generating random solutions for constraint satisfaction problems
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A BNF-based automatic test program generator for compatible microprocessor verification
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VLIW: a case study of parallelism verification
Proceedings of the 42nd annual Design Automation Conference
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Automatic functional test program generation for microprocessor verification
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Scheduling-based test-case generation for verification of multimedia SoCs
Proceedings of the 43rd annual Design Automation Conference
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
IEEE Transactions on Computers
Design fault directed test generation for microprocessor validation
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A framework for the validation of processor architecture compliance
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Constraint-based random stimuli generation for hardware verification
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Using linear programming techniques for scheduling-based random test-case generation
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Constraint patterns and search procedures for CP-based random test generation
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Constraint-based local search for the automatic generation of architectural tests
CP'09 Proceedings of the 15th international conference on Principles and practice of constraint programming
Testing continuous double auctions with a constraint-based oracle
CP'10 Proceedings of the 16th international conference on Principles and practice of constraint programming
Functional test generation with distribution constraints
HVC'09 Proceedings of the 5th international Haifa verification conference on Hardware and software: verification and testing
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Threadmill: a post-silicon exerciser for multi-threaded processors
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Engineering Applications of Artificial Intelligence
Constraint programming with arbitrarily large integer variables
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Path-Based system level stimuli generation
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A new test-generation methodology for system-level verification of production processes
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Automatic generation of test programs plays a major role in the verification of modern processors and hardware systems. In this paper, we formulate the generation of test programs as a constraint satisfaction problem and develop techniques for dealing with the challenges we face, most notably: huge variable domains (e.g., magnitude of 264) and the need to randomly generate "well distributed" samplings of the solution space. We describe several applications of our method, which include specific test generators targeted at various parts of a design or stages of the verification process.