Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic Vector Generation Using Constraints and Biasing
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Generating random solutions for constraint satisfaction problems
Eighteenth national conference on Artificial intelligence
Computing the minimum DNF representation of boolean functions defined by intervals
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing the minimum DNF representation of Boolean functions defined by intervals
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
A scalable and nearly uniform generator of SAT witnesses
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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