Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic Model Checking
Constraint Slving for Test Case Generation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Commercial Design Verification: Methodology and Tools
Proceedings of the IEEE International Test Conference on Test and Design Validity
Nuts and bolts of core and SoC verification
Proceedings of the 38th annual Design Automation Conference
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Constraining and biasing are frequently used techniques toenhance the quality of randomized vector generation. In this paper,we present a novel method that combines constraints and input biasingin automatic bit-vector generation for block-level functionalverification of digital designs, which is implemented in a toolcalled SimGen. Vector generation in SimGen is confined to a legalinput space that is defined by constraints symbolically representedin Binary Decision Diagrams (BDDs). A constraint involving statevariables in the design defines a state-dependent legal input space.Input biasing can also depend on the state of the design. The effectof constraints and input biasing are combined to form what we calledthe constrained probabilities of input vectors. An algorithm isdeveloped to efficiently generate input vectors on-the-fly duringsimulation. The vector generation is a one-pass process, i.e., nobacktracking or retry is needed. Also, we describe methods ofminimizing the constraint BDDs in an effort to reduce thesimulation-time overhead of SimGen. Furthermore we discuss theapplication of SimGen to a set of commercial design blocks.