Digital Technical Journal - Special 10th anniversary issue
Verifying a Multiprocessor Cache Controller Using Random Test Generation
IEEE Design & Test
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Verification of configurable processor cores
Proceedings of the 37th Annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Automatic Vector Generation Using Constraints and Biasing
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Pre-silicon verification of the Alpha 21364 microprocessor error handling system
Proceedings of the 38th annual Design Automation Conference
A simulation-based method for the verification of shared memory in multiprocessor systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Formal Verification of the Alpha 21364 Network Protocol
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Coverage-oriented verification of banias
Proceedings of the 40th annual Design Automation Conference
Increased Information Flow Needs for High-Assurance Composite Evaluations
IWIA '04 Proceedings of the Second IEEE International Information Assurance Workshop (IWIA'04)
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Depth-driven verification of simultaneous interfaces
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Testing implementations of transactional memory
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Energy-efficient dynamic instruction scheduling logic through instruction grouping
Proceedings of the 2006 international symposium on Low power electronics and design
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Energy-efficient dynamic instruction scheduling logic through instruction grouping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 50th Annual Design Automation Conference
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DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features a 500 MHz clock speed and a high-bandwidth system interface that channels up to 5.3 Gbytes/second of cache data and 2.6 Gbytes/second of main-memory data into the processor. Simulation-based functional verification was performed on the logic design using implementation-directed, pseudo-random exercisers, supplemented with implementation-specific, hand-generated tests. Extensive functional coverage analysis was performed to grade and direct the verification effort. The success of the verification effort was underscored by first prototype chips which were used to boot multiple operating systems across several different prototype systems.