DAC '98 Proceedings of the 35th annual Design Automation Conference
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Language-Based High Level Transaction Extraction on On-chip Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A mixed-signal verification kit for verification of analogue-digital circuits
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, andsimulation-coverage analyzer. This approach combines the conventional transaction level language such as C and the signal level language based on our previously developed Component Wrapper Language (CWL). This approach is based on two concepts. The first one is a complete separation between transaction-level verification and signal-level verification for generating suitable verification suites in each design phase. The second one is the quick generation of signal-level verification suites from the original specification written in CWL. Experimental results show that our approach should yield much shorter verification periods versus conventional methods.