Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 37th Annual Design Automation Conference
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Improving Gate Level Fault Coverage by RTL Fault Grading
Proceedings of the IEEE International Test Conference on Test and Design Validity
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A component-based specification approach for embedded systems using FDTs
SAVCBS '05 Proceedings of the 2005 conference on Specification and verification of component-based systems
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Towards Equivalence Checking Between TLM and RTL Models
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Towards RTL test generation from SystemC TLM specifications
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
A Novel Simulation Fault Injection Method for Dependability Analysis
IEEE Design & Test
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations
SSIRI '09 Proceedings of the 2009 Third IEEE International Conference on Secure Software Integration and Reliability Improvement
Functional qualification of TLM verification
Proceedings of the Conference on Design, Automation and Test in Europe
Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A test evaluation technique for VLSI circuits using register-transfer level fault modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Functional verification techniques based on fault injection and simulation at register-transfer level (RTL) have been largely investigated in the past years. Although they have various advantages such as scalability and simplicity, they commonly suffer from the low speed of the cycle-accurate RTL simulation. On the other hand, Transaction-level modeling (TLM) allows a simulation speed sensibly faster than RTL. This article presents FAST, a framework to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. FAST abstracts RTL models injected with any RTL fault model into equivalent injected TLM models thus allowing a very fast fault simulation at TLM level. The article also presents FAST-DT, a new bit-accurate data type library integrated in the framework that allows a further improvement of the simulation speed-up. Finally, the article shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been performed on several designs of different size and complexity to show the methodology effectiveness.