Towards RTL test generation from SystemC TLM specifications

Authors:
Mingsong Chen; Prabhat Mishra; Dhrubajyoti Kalita
Affiliations:
Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA;Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA;Intel Corporation 1900 Prairie City Road, Folsom, CA 95630, USA
Venue:
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Year:
2007

Citing 0
Cited 3

Automatic RTL Test Generation from SystemC TLM Specifications

ACM Transactions on Embedded Computing Systems (TECS)
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction

Journal of Electronic Testing: Theory and Applications
A HW/SW co-verification framework for SystemC

ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems

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Abstract

SystemC Transaction Level Modeling (TLM) is widely used to reduce the overall design and validation effort of complex System-on-Chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial re- sults using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as in- consistencies in the implementation.