VHDL & Verilog compared & contrasted—plus modeled example written in VHDL, Verilog and C
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimizations for a simulator construction system supporting reusable components
Proceedings of the 40th annual Design Automation Conference
SAGA: SystemC acceleration on GPU architectures
Proceedings of the 49th Annual Design Automation Conference
From RTL IP to functional system-level models with extra-functional properties
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 50th Annual Design Automation Conference
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, System Verilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2x faster than VHDL for RTL models. We found that SystemC results in 10x slower RTL models than HDLs and surprisingly results in 2.6x slower TLM1 PV models than System Verilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest.