Proceedings of the conference on Design, automation and test in Europe
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
A Novel Simulation Fault Injection Method for Dependability Analysis
IEEE Design & Test
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Abstraction of RTL IPs into embedded software
Proceedings of the 47th Design Automation Conference
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Parallel Cycle Based Logic Simulation Using Graphics Processing Units
ISPDC '10 Proceedings of the 2010 Ninth International Symposium on Parallel and Distributed Computing
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
A test evaluation technique for VLSI circuits using register-transfer level fault modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
On the automatic generation of GPU-oriented software applications from RTL IPs
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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This paper presents FAST-GP, a framework for functional verification of RTL designs, which is based on fault injection and parallel simulation on GP-GPUs. Given a fault model, the framework translates the RTL code into an injected C code targeting NVIDIA GPUs, thus allowing a very fast parallel automatic test pattern generation and fault simulation. The paper compares different configurations of the framework to better exploit the architectural characteristics of such GP-GPUs (such as thread synchronization, branch divergence, etc.) by considering the architectural characteristics of the RTL design under verification (i.e., complexity, size, number of injected faults, etc.). Experimental results have been conducted by applying the framework to different designs, in order to prove the methodology effectiveness.