Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Systemic Embedded Software Generation from SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Locality-Aware Process Scheduling for Embedded MPSoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
Towards Equivalence Checking Between TLM and RTL Models
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
On the automatic synthesis of parallel SW from RTL models of hardware IPs
Proceedings of the great lakes symposium on VLSI
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis
Proceedings of the 50th Annual Design Automation Conference
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded systems evolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Journal of Electronic Testing: Theory and Applications
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High performance provided by multi-processor System-on-Chips (MPSoCs) often induces designers to choose customized processors to execute specific functions rather than using dedicated hardware. On the other hand, reuse of pre-designed and pre-verified IP cores is the key strategy to meet time-to-market while at the same time reducing the error risk during the development of MPSoC designs. In this context, it becomes convenient to translate an existent RTL IP description, originally dedicated to implement an HW component, into pure SW code (i.e., C/C++) to be executed by one or more processors of the MPSoC. This work proposes a methodology to automatically generate SW code by abstracting RTL IP models implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate many implementation details typical of the HW descriptions, in order to improve the performance of the generated code.