Avoiding conflict misses dynamically in large direct-mapped caches
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Compiler optimizations for improving data locality
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Data transformations for eliminating conflict misses
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Locality-conscious process scheduling in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Data Space Oriented Scheduling in Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 20th annual conference on Integrated circuits and systems design
Assessing task migration impact on embedded soft real-time streaming multimedia applications
EURASIP Journal on Embedded Systems - Operating System Support for Embedded Real-Time Applications
Abstraction of RTL IPs into embedded software
Proceedings of the 47th Design Automation Conference
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
Journal of Systems Architecture: the EUROMICRO Journal
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Utilizing on-chip caches in embedded multiprocessor-system-on-a-chip (MPSoC) basedsystems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at hardware and compilation levels, operating system (OS) can also play major role as it sees the global access pattern information across applications. This paper proposes a cache-conscious OS process scheduling strategy based on data reuse. The proposed scheduler implements two complementary approaches. First, the processes that do not share any data between them are scheduled at different cores if it is possible to do so. Second, the processes that could not be executed at the same time (due to dependences) but share data among each other are mapped to the same processor core so that they share the cache contents. Our experimental results using this new data locality aware OS scheduling strategy are promising, and show significant improvements in task completion times.