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IEEE Transactions on Computers
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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Unified Methods for VLSI Simulation and Test Generation
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Design Verfication and Reachability Analysis Using Algebraic Manipulation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Sequential Machines: Selected Papers
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Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
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Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
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DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Generating finite state machines from abstract state machines
ISSTA '02 Proceedings of the 2002 ACM SIGSOFT international symposium on Software testing and analysis
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
RT-level TPG Exploiting High-Level Synthesis Information
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testability analysis and ATPG on behavioral RT-level VHDL
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SystemC
Constraint-Based Verification of Parameterized Cache Coherence Protocols
Formal Methods in System Design
A technique to generate feasible tests for communications systems with multiple timers
IEEE/ACM Transactions on Networking (TON)
A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models
IEEE Transactions on Computers
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
An EFSM-based approach for functional ATPG
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Automatic generation of symbolic model for parameterized synchronous systems
Journal of Computer Science and Technology
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
EFSM Manipulation to Increase High-Level ATPG Effectiveness
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A framework for the functional verification of systemC models
International Journal of Parallel Programming
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Proceedings of the conference on Design, automation and test in Europe
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Implementation of supervisory control using extended finite-state machines
International Journal of Systems Science
Processor Description Languages
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Proceedings of the 2006 International Conference on Privacy, Security and Trust: Bridge the Gap Between PST Technologies and Business Services
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abstraction of RTL IPs into embedded software
Proceedings of the 47th Design Automation Conference
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Proceedings of the Conference on Design, Automation and Test in Europe
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
Journal of Electronic Testing: Theory and Applications
Information and Software Technology
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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
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CSR'07 Proceedings of the Second international conference on Computer Science: theory and applications
Computers in Biology and Medicine
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Proceedings of the International Conference on Computer-Aided Design
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We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing, or power estimation. A high-level description of the circuit in VHDL or C is assumed available. Our method automatically transforms the high-level description of a circuit in VHDL or C into an extended finite state machine (EFSM) model that is used to generate functional vectors. The EFSM model is a generalization of the traditional state machine model. It is a compact representation of models with local data variables and preserves many nice properties of a traditional state machine model. The theoretical background of the EFSM model is addressed in this article. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using our prototype system.